Modern microprocessors may include two or more processor cores on a single semiconductor device. Such microprocessors may be called multi-core processors. The use of these multiple cores may improve performance beyond that permitted by using a single core. Each core may include its own level one data and instruction cache, and there may additionally be a level two cache on the device.
In order to enhance performance, the cache locations in the level one data caches may be of a length selected in response to the expected data types. Limitation on device size may permit either a larger number of cache locations of a shorter length, or a smaller number of cache locations of a longer length. When the expected data has great spatial locality (e.g. the data tend to be located in contiguous areas of memory), performance may be enhanced by using a smaller number of cache locations of the longer length. At the other extreme, when the expected data has little spatial locality (e.g. the data may be randomly or pseudo-randomly scattered throughout memory), performance may be enhanced by using a larger number of cache locations of shorter length.
It is possible to design level one data caches with several groups of cache locations, each group containing cache locations of a different length. This may permit enhanced performance across various kinds of expected data. Additionally, a particular piece of data may simultaneously be present in multiple groups of cache locations, again to permit enhanced performance. However, most cache coherency engines operate at the granularity of the cache location/cache line size. For the sake of simplicity these are designed to support a common cache location/cache line size. Therefore a cache coherency engine intended for use with caches of varying cache location length is a design issue, especially when an existing cache coherency protocol would preferably be used without fundamental redesign.